Process variations can cause component characteristics on a semiconductor device to greatly vary. A static random access memory (SRAM) cell can store a logic one or a logic zero level. A logic one may have a current path through a p-channel insulated gate field effect transistor (IGFET) and a logic zero may have a current path through an n-channel IGFET during a read operation.
The electrical performance characteristics of the different transistor device types in an integrated circuit are subject to variations stemming from factors such as manufacturing process drift, temperature and other effects that result in speed, minimum supply voltage and other variability constraints at the chip level. Such fluctuations are typically comprehended in a “design window” where a certain degree of assumed range from performance (speed) midpoint is built in to those rules and tools as margin from which the integrated circuits are designed. However, design window constraint by definition places limitations on the degree of freedoms for design. Design windows generally comprehend transistor “fast” and “slow” corners within which circuit designers would be constrained in building reliable circuits, for instance, incorporating design redundancy, set timing conservatively and other factors that affect a design implementation of any starting point architecture.